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[ ak 7707 ] 016011589 - e - 00 - pb 20 16/11 - 1 - 1. general description the ak77 07 is a highly integrated digital signal processor, including 6 stereo sampling rate convertors supporting sampling frequency up to 192khz, a dir, a dit and two types of dsps for audio and voice process ing . the dsp1 supports a 295 mhz core and is optimized for c - language support. dsp2 and dsp3 have 4608 step/fs (when fs=48khz) processing power. the ak7707 is able to process multiple sample rates simulta neously. this function is ideal for full bandwidth audio and voice processing, such as hands - free function along with audio. this simultaneous processing is enabled because the two types of dsps can work on different but synchronized sampling frequencies. t he ak77 07 is a ram based ds p , so it can be freely programm ed for user requirements, such as acoustic effects and proprietary high performance hands - free function. the ak77 07 is available in a space saving 64 - pin ht qfp package. 2. features ? dsp1( tensilica h ifi2): - word length: 64 - bit - operation clock: 294.912 mhz (dsp1 fast mode ) - iram: 128kb - dram: 384kb - gpio: 8 ports - spi control master port x 1 - jtag for on - chip debugging - independent power management ? dsp2, 3(akm dsp) - word length: 28 - bit (data ram: simple floating point ) - operation clock 221.184mhz (4608 steps, fs= 48khz , dsp2/3 fast mode ) - multiplier: 24 x 24 48 - bit ( double precision arithmetic available ) - divider: 24 / 24 24 - bit ( floating point normalization function ) - alu: 52 - bit arithmetic operation (with overflow margin 4 - bit) - program ram (pram): 10kword x 36 - bit (dsp2+dsp3 total) - coefficient ram (cram): 10kword x 24 - bit (dsp2+dsp3 total) - data ram (dram): 10kword x 28 - bit (d s p2+dsp3 total) - delay ram(dlram): 24kword x 28 - bit (dsp2+dsp3 total) - jx pins (interrupt) - independent power management function ? src - 2ch x 6 - fsi = 8khz ~ 192khz, fso= 8khz ~ 192khz (fso/fsi= 0.167 ~ 6.0) multi core dsp with src ak7707
[ a k7707 ] 016011589 - e - 00 - pb 20 16/11 - 2 - ? dir - s/pdif, iec60958, aes/ebu , eiaj cp1201 - amplifier: 2 i nputs selector - de - e m phasis f i lter (32, 44.1, 48, 96khz, on/off function) - non - pcm data stream detection function - dts - cd data stream detection function - sampling frequency detection function (32khz, 4 4.1 khz, 48khz, 88.2khz 96khz ) - unlock & parity error detection function - validity detection register read back function - 42 - bit channel status buffer - q - sub code buffer fo r cd bit stream ? dit - s/pdif, iec60958, aes/ebu, eiaj cp1201 compatible - 24 - bit stereo output ? d igital interfaces - digital input 8 - port (max. 64ch, tdm mode) - digital output 8 - port (max. 64ch, tdm mode) - independent lrck/bick in/output port x 5 lines - data format: msb 32, 24 - bit/ lsb24, 20, 16 - bit/ i 2 s - shot/ long frame - tdm in/output mode - digital microphone input ports (2ch x 2 lines) ? digital mixer circuit ? pll circuit ? p interface : spi (7mhz max.) / i 2 c (1mhz fast mode plus) ? power supply : digital: vdd12: 1.14v ~ 1.3v (typ. 1.2v) i/f: vdd33: 3.13v ~ 3.47v (typ. 3.3v) tvdd1: 1.7v ~ 3.47v (typ. 3.3v) tvdd2: 1.7v ~ 3.47v (typ. 3.3v) avdd: 3.13v ~ 3.47v (typ. 3.3v) ? operation temperature range: ta= - 40 ~ 85 o c ? package: 64 - pin ht qfp (10mm x 10mm, 0.5mm pitch)
[ a k7707 ] 016011589 - e - 00 - pb 20 16/11 - 3 - 3. table of contents 1. general description ................................ ................................ ................................ .......................... 1 2. features ................................ ................................ ................................ ................................ ............ 1 3. table of contents ................................ ................................ ................................ .............................. 3 4. block diagram and functions ................................ ................................ ................................ ........... 4 device block diagram ................................ ................................ ................................ ........................ 4 dsp1 block diagram ................................ ................................ ................................ ......................... 5 dsp2 b lock diagram ................................ ................................ ................................ ......................... 6 dsp3 block diagram ................................ ................................ ................................ ......................... 7 5. pin configurations and functions ................................ ................................ ................................ ..... 8 pin layout ................................ ................................ ................................ ................................ .......... 8 pin functions ................................ ................................ ................................ ................................ ...... 9 handling the unused pins ................................ ................................ ................................ ................ 12 relationship between digital power supply and input/output pins ................................ ................ 12 power - down pin status ................................ ................................ ................................ .................... 13 6. absolute maximum ratings ................................ ................................ ................................ ............ 14 7. recommended operating conditions ................................ ................................ ............................ 15 8. electrical characteristics ................................ ................................ ................................ ................. 16 src ................................ ................................ ................................ ................................ .................. 16 spdif characteristics ................................ ................................ ................................ ...................... 17 di gital micrephone interface ................................ ................................ ................................ ............ 17 current consumption ................................ ................................ ................................ ....................... 17 9. digital filter characteristics ................................ ................................ ................................ ............ 18 src block ................................ ................................ ................................ ................................ ........ 18 10. dc character istics ................................ ................................ ................................ .......................... 20 dc characteristics ................................ ................................ ................................ ........................... 20 11. switching characteristics ................................ ................................ ................................ ................ 21 system clock ................................ ................................ ................................ ................................ ... 21 power down ................................ ................................ ................................ ................................ ..... 21 serial data interface (sdin1~sdin8, sdout1~sdout8) ................................ ............................ 22 spi interface ................................ ................................ ................................ ................................ ..... 25 i 2 c interface ................................ ................................ ................................ ................................ ...... 27 master spi interface ................................ ................................ ................................ ........................ 28 jtag interface ................................ ................................ ................................ ................................ . 28 12. recommen ded external circuits ................................ ................................ ................................ .... 29 connection diagram ................................ ................................ ................................ ........................ 29 peripheral circuit ................................ ................................ ................................ .............................. 30 13. pack age ................................ ................................ ................................ ................................ .......... 31 outline dimensions ................................ ................................ ................................ .......................... 31 material and lead finish ................................ ................................ ................................ .................. 31 marking ................................ ................................ ................................ ................................ ............. 32 14. ordering guide ................................ ................................ ................................ ................................ 32 ordering guide ................................ ................................ ................................ ................................ . 32 important notice ................................ ................................ ................................ .......................... 33
[ a k7707 ] 016011589 - e - 00 - pb 20 16/11 - 4 - 4. block diagram and functions device block diagram figure 1 . ak7707 device block diagram scl / sclk i2cfil / si csn sda/so testi2 tvdd1 clko clkgen & cont xti xto pdn wdterrn1 dsp1 gpio32 din104 din106 dout104 din105 dout106 dout105 din103 dout101 din102 dout103 dout102 din101 dsp3 din304 din306 dout304 din305 dout306 dout305 din303 dout301 din302 dout303 dout302 din301 src1~4 tvdd2 micif & ctrl bicka lrcka bickb lrckb lrckc bickc bickd/dmclk2 lrckd/dmclk1 bicke lrcke sdin1 sdin2 sdin3 sdin4/dmdat1 sdin5/dmdat2 sdin6 / rx1 serial if serial if serial if serial if serial if serial if serial if serial if serial if sdout1 sdout2 sdout5 / gpo3 serial if sdout4 clk serial signal bus serial if sdout3 / gpo2 vss 6 vdd33 serial if sdout6 / dit dit dir hifi2 core ak77core rx0 sto / rdy testi1 src5~6 dsp i/o if gpio00 / sdin7 gpio01 / sdout7 gpio02 / sdin8 gpio03 / sdout8 esdi / gpio06 esdo / gpio04 esclk / gpio05 ecso / gpio07 vdd12 3 pll testa1 dirint / rdy / gpo0 testa2 tdo / gpo1 tms / jx2 tck / jx1 tdi / jx3 trst / jx0 32bit fifo x 16 dout110 dout112 dout111 dout107 dout109 dout108 din110 din112 din111 din109 din108 din107 mixer a,b wdterrn2 dsp2 din204 din206 dout204 din205 dout206 dout205 din203 dout201 din202 dout203 dout202 din201 gp20,gp21 jx20~23 sele dout113 dout114 dout115 dout116 din114 din116 din115 din113 merger1~16 divider1~8 avdd wdterrn3 gp30,gp31 jx30~33
[ a k7707 ] 016011589 - e - 00 - pb 20 16/11 - 5 - dsp1 block diagram figure 2 . dsp 1 block diagram dsp1 (hifi2) c ore iram0 128kb dram0 128kb dram1 256kb xlmi - arbiter audio i/o buffer 1/2 2kb slave - spi i/o buffer 2kb watchdog timer 32 - bit master - spi i/o buffer 256 - bit status 24 - bit jtag slave - spi slave - spi slave - spi gpio interrupt audio - bus slave - spi master - spi
[ a k7707 ] 016011589 - e - 00 - pb 20 16/11 - 6 - dsp2 block diagram figure 3 . dsp2 block diagram tmp 8 28bit sdout3 cp0, cp1 dp0, dp1 d ata ram (dram) 6~8 k w x 2 8 - b it (24. 4 f) mpx 2 4 mpx2 4 x y multiply 2 4 x 2 4 48 - b it microcomputer i/f control program ram (pram) 6~8 k w x 36 - b it dec pc s tack : 8 l evel s (m ax . ) mul dbus shift a b alu 52 - b it o verflow margi n: 4 - b it dr0 ? 3 over flow data generator division 24 ? 24 2 4 peak detector serial i/f cbus ( 2 4 - b it) dbus(2 8 - b it) 4 8 - b it 28 - b it 48 - b it 52 - b it 52 - b it 12~24 k w x 2 8 - b it ( 24. 4 f) p tmp (lifo) 6 x 2 8 - b it d l p0, d l p1 52 - b it tmp 12 x 28 - b it ofr eg 64 w x 1 5 - b it d e l ay ram (dlram ) coefficient ram (cram) 6~8 k w x 2 4 - b it pointer 32 - bit x fifo1 6 dtmp ( connect to dsp 3 ) 2 x 32 - b it din6 2 x 32 - b it din5 2 x 32 - b it din4 2 x 32 - b it din3 2 x 32 - b it din2 2 x 32 - b it din1 2 x 32 - b it dout6 2 x 32 - b it dout5 2 x 32 - b it dout4 2 x 32 - b it dout3 2 x 32 - b it dout2 2 x 32 - b it dout1
[ a k7707 ] 016011589 - e - 00 - pb 20 16/11 - 7 - dsp 3 block diagram figure 4 . dsp 3 block diagram tmp 8 28bit sdout3 cp0, cp1 dp0, dp1 d ata ram (dram) 2~4 k w x 2 8 - b it (24. 4 f) mpx 2 4 mpx2 4 x y multiply 2 4 x 2 4 48 - b it program ram (pram) 2~4 k w x 36 - b it dec pc s tack : 8 l evel s (m ax . ) mul dbus shift a b alu 52 - b it o verflow margin: 4 - b i t dr0 ? 3 over flow data generator division 24 ? 24 2 4 peak detector serial i/f cbus ( 2 4 - b it) dbus(2 8 - b it) 4 8 - b it 28 - b it 48 - b it 52 - b it 52 - b it 0 ~12 k w x 2 8 - b it ( 24. 4 f) p tmp (lifo) 6 x 2 8 - b it d l p0, d l p1 52 - b it tmp 12 x 28 - b it ofr eg 64 w x 1 5 - b it d e l ay ram (dlram ) coefficient ram (cram) 2~4 k w x 2 4 - b it pointer 32 - bit x fifo1 6 dtmp ( connect to dsp 2 ) 2 x 32 - b it din6 2 x 32 - b it din5 2 x 32 - b it din4 2 x 32 - b it din3 2 x 32 - b it din2 2 x 32 - b it din1 2 x 32 - b it dout6 2 x 32 - bit dout5 2 x 32 - bit dout4 2 x 32 - bit dout3 2 x 32 - bit dout2 2 x 32 - bit dout1 microcomputer i/f control
[ a k7707 ] 016011589 - e - 00 - pb 20 16/11 - 8 - 5. pin configurations and functions pin layout vss3 tvdd1 clko vdd12 (top view) 64pin lqfp gpio02 gpio03 *** framed pin names indicate that they are pull - down pins 1 49 gpio01 i2cfil / si testi2 tms / jx2 vss6 trs t / jx0 testa2 rx0 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 vdd33 sdin6 / rx1 avdd vss5 input output i / o power gpio07 gpio06 csn gpio04 gpio05 pdn tdo / gpo1 vss2 tvdd1 avdd vdd33 sdout7 sdin8 sdout8 esdo esclk esdi ecso tck / jx1 vss1 sdout4 sdout5 / gpo3 vdd12 bicke lrcke dirint / rdy / gpo0 sdin5 / dmat2 sdin4 / dmat1 sdout3 / gpo2 bickd lrckd sdin3 lrckc dmclk1 dmclk2 sele vss4 vdd12 sdin1 bicka lrcka sdout1 sdin2 sdout2 lrckb bickb xti xto sto / rdy so sda tvdd2 gpio00 sdin7 bickc tvdd2 sdout6 / dit tdi / jx3 testi1 scl / sclk testa 1 preceded pin names are default pins. (default example: 1 - pin sdout6, 32 - pin scl, 33 - pin sda and 64 - pin tdi )
[ a k7707 ] 016011589 - e - 00 - pb 20 16/11 - 9 - pin functions no. pin name i/o function supply 1 sdout6 o serial data output 6 vdd33 dit o dit output 2 testi1 i test input ( pulled - down ) connect this pin to l vdd33 3 bicke i/o serial bit clock e ( input pulled - down ) vdd33 4 lrcke i/o lr channel select clock e ( input pulled - down ) vdd33 5 sdout5 o serial data output 5 vdd33 gpo3 o general output 3 (dsp3 - gp 1) 6 dirint o dir interrupt output vdd33 rdy o rdy pin gpo0 o general output 0 (dsp2 - gp 0) 7 vdd12 - digital power supply t yp . 1.2v ( 1.14v ~ 1.3 v ) - 8 vss1 - ground 1 0v - 9 sdin5 i serial data in put 5 tvdd 2 dmdat2 i data2 p in for digital microphone 10 sdin4 i serial data in put 4 tvdd2 dmdat1 i data1 p in for digital microphone 11 bickd i/o serial bit clock d ( input pulled - down ) tvdd2 dmclk2 o clock out put 2 for digital microphone 12 lrckd i/o lr channel select clock d ( input pulled - down ) tvdd2 dmclk1 o clock output 1 for digital microphon e 13 sdout4 o serial data output 4 tvdd2 14 sdout3 o serial data output 3 tvdd2 gpo2 o general output 2 (dsp 3 - gp 0) 15 sdin3 i serial data in put 3 tvdd2 16 lrckc i/o lr channel select clock c ( input pulled - down ) tvdd2 17 bi ck c i/o serial bit clock c ( input pulled - down ) tvdd2 18 gpio00 i/o dsp1 gpio pin controlled by dsp1 program. ( input pulled - down ) tvdd2 sdin7 i serial data in put 7 19 gpio01 i/o dsp1 gpio pin controlled by dsp1 program. ( input pulled - down ) tvdd2 sdout7 o serial data output 7 20 tvdd2 - digital power supply 2 t yp . 3.3v ( 1.7v ~ 3. 47 v ) - 21 vss2 - ground 2 0v - 22 vdd12 - digital power supply 12 pin t yp . 1.2v ( 1.14v ~ 1.3 v ) - 23 gpio02 i/o dsp1 gpio 2 pin controlled by dsp1 program. ( input pulled - down ) tvdd2 sdin8 i serial data in put 8 ( pulled - down ) 24 gpio03 i/o dsp1 gpio pin controlled by dsp1 program. ( input pulled - down ) tvdd2 sdout8 o serial data output 8 25 esdo o spi control data output for external devices ( connect to the si pin of external device ) ( pulled - down ) tvdd2 gpio04 i/o dsp1 gpio 4 pin controlled by dsp1 program. ( pulled - down )
[ a k7707 ] 016011589 - e - 00 - pb 20 16/11 - 10 - no. pin name i/o function supply 26 esclk o spi control data output for external devices ( connect to the sclk pin of external device ) tvdd2 gpio05 i/ o dsp1 gpio 5 pin controlled by dsp1 program. ( input pulled - down ) 27 esdi i spi control data input for external devices ( connect to the so pin of external device ) ( pulled - down ) tvdd2 gpio06 i/o dsp1 gpio 6 pin controlled by dsp1 program. ( input pulled - down ) 28 ecso o spi control data output for external devices ( connect to the cs pin of external device ) tvdd2 gpio07 i/o dsp1 gpio 7 pin controlled by dsp1 program. ( input pulled - down ) 29 pdn i power down n pin ? ? 2 c mode : bus address pin for i 2 c interface ? ? ? 2 c interface mode select input ? = l ? i2cfil = h 2 c interface tvdd1 sclk i serial data clock input for spi interface 33 sda i/o sda pin for i 2 c interface tvdd1 so o serial data output for spi interface 34 sto o status output tvdd1 rdy o rdy pin 35 sele i self - boot enable tvdd1 36 clko o clock output tvdd1 37 vss3 - ground 3 pin 0v - 38 tvdd1 - digital io power supply 1 t yp . 3.3v ( 1.7v ~ 3. 47 v ) - 39 bickb i/o serial bit clock b ( input pulled - down ) tvdd1 40 lrckb i/o lr channel select clock b ( input pulled - down ) tvdd1 41 sdout2 o serial data output 2 tvdd1 42 sdin2 i serial data in put 2 tvdd1 43 vss4 - ground 4 0v - 44 vdd12 - digital power supply 12 t yp . 1.2v ( 1.14v ~ 1.3 v ) - 45 sdin1 i serial data in put 1 tvdd1 46 sdout1 o serial data output 1 tvdd1 47 lrck a i/o lr channel select clock a ( input pulled - down ) tvdd1 48 bicka i/o serial bit clock a ( input pulled - down ) tvdd1
[ a k7707 ] 016011589 - e - 00 - pb 20 16/11 - 11 - no. pin name i/o function supply 49 xto o oscillation circuit out put ? ? ? ?
[ a k7707 ] 016011589 - e - 00 - pb 20 16/11 - 12 - handling the unused pins unused i/o pins must be connected appropriately. classification pin name (pin no.) setting digital sdout6/dit(1), sdout5/gpo3 (5), dirint/ rdy/ gpo0(6), sdout4(13), sdout3/gpo2(14), esdo/gpio04(25),esclk/gpio05(26), ecso/gpio07(28),so/sda(33), sto/rdy(34), clko(36), sdout2(41), sdout1(4 6 ), tdo/gpo1(6 2 ) open bicke(3), lrcke(4), sdin5/dmdat2(9), sdin4/dmdat1(10), bickd/dmclk2(11), lrckd/dmclk1(12), sdin3(15), lrckc(16), bickc(17), gpio00/sdin7(18), gpio01/sdout7(19), gpio02/sdin8(23), gpio03/sdout8(24), esdi/gpio06(27), csn(30), i2cfil/si(31), scl/sclk(32), sele(35), bickb(39), lrckb(40), sdin2(42 ), sdin1(45), lrcka(47), bicka(48), testi1(55), rx0(56), testi2(57), sdin6/rx1(59), trst/jx0(60), tck/jx1(61), tms/jx2(63), tdi/jx3(64), connect to vss 1~ 4, 6 analog xto(49), testa1(53 ) ,testa2(54) open xti(50) connect to vss 5 table 1 . handling of unused pins relationship between digital power supply and input/ output pins power supply input/output pins tvdd1 (1.7~3.3v) bi ck a(48) , lr ck a(47) , sdout1(46), sdin1(45), sdin2(42), sdout2(41), lrckb(40), bickb(39), clko(36), sele(35),sto/rdy(34), sda/so(33), scl/sclk(32), i2cfil/si(31), csn(30), pdn(29) tvdd2 (1.7~3.3v) sdin5/dmdat2(9),sdin4/dmdat1(10),bickd/dmclk2(11),lrckd/dmclk1(12), sdout4(13),sdout3/gpo2(14),sdin3(15),lrckc(16),bickc(17), gpio00/sdin7(18),gpio01/sdout7(19),gpio02/sdin8(23),gpio03/sdout8(24), esdo/gpio04(25), esclk/gpio05(26), esdi/gpio06(27), ecso/gpio07(28) vdd33 (3.3v) testi2(55), rx0(56) , sdin6/rx1(59), trst/jx0(60), tck/jx1 ( 61), tdo/gpo1(62), tms/jx2(63) , tdi/jx3(64) , sdout6/dit(1) , testi1(2), bicke(3) , lrcke(4) , sdout5/gpo3(5),dirint/gpo0(6) avdd (3.3v) xto(49), xti(50), testa1(53), testa2 (54) table 2 . relationship between digital power supply and input/output pins
[ a k7707 ] 016011589 - e - 00 - pb 20 16/11 - 13 - power - down pin status no pin name i/o power - down status no pin name i/o power - down status 1 sdout 6 o l l l l h
[ a k7707 ] 016011589 - e - 00 - pb 20 16/11 - 14 - 6. absolute maximum ratings ( vss1 ~6 = 0v ; * 1 ) parameter symbol m in . m ax . unit power supply analog digital1(core) digital 2 (i/f) digital 3 (i/f) digital4(i/f) difference ( vss1 ~ vss 6 ) ( * 1 ) avdd vdd 12 tvdd1 tvdd2 vdd33 gnd warning: operation at or beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these ext remes.
[ a k7707 ] 016011589 - e - 00 - pb 20 16/11 - 15 - 7. recommended operating conditions ( vss1 ~6 = 0v ; * 1 ) parameter symbol m in . t yp . m ax . unit power supply analog digital (3.3v, i/f) digital ( 1.2v core) digital (i/f) digital (i/f) avdd vdd33 vdd 12 tvdd1 tvdd2 3.13 3.13 1.14 1.7 1.7 3.3 3.3 1.2 3.3 3 .3 3.47 3.47 1.3 3. 47 3. 47 v v v v v notes: * 6 . tvdd2 must be supplied from the first regulator that is power ed up. * 7 . all power supply pins must be connected to the power supply. * 8 . the pdn pin should be held l when power is supplied. the pdn pin is allowed to be h after all power supplies are applied and settled. * 9 . the power up sequence must be executed from the beginning when changing power supply level of the tvdd1 and tvdd2. (e.g. 1.8v 3.3v) * 10 . d o not turn off the power supply of the ak77 07 with the power supply of the surrounding device turned on. when using the i 2 c interface, pu ll - up resistors of sda and scl pins should be connected to tvdd 1 or less voltage . warning: akm assumes no responsibility for the usage beyond the conditions in the datasheet.
[ a k7707 ] 016011589 - e - 00 - pb 20 16/11 - 16 - 8. electrical characteristics src ( ta= 2 5 ? c ; vdd12= 1.2v, avdd= vdd33= tvdd1= tvdd2 = 3.3v ; vss1 ~ 6 = 0v ; s i gnal frequency = 1khz; 24 - bit data ; measurement frequency =20hz ~ fso/ 2 ) src parameter symbol m in . t yp . m ax . unit resolution 24 bit input sample rate fsi 8 192 ( * 11 ) khz output sample rate fso 8 19 2 khz thd+n (input=1khz, 0dbfs) audio mode fso/fsi= 192 khz/48khz fso/fsi= 44.1 khz/48khz fso/fsi= 48 khz/ 88.2 khz fso/fsi= 48 khz/ 96 khz fso/fsi= 44.1 khz/ 96 khz fso/fsi= 48 khz/ 192 khz fso/fsi= 8 khz/ 48 khz voice mode fso/fsi= 24 khz/ 32 khz fso/fsi= 16 khz/ 24 khz fso/fsi= 24 khz/ 44.1 khz fso/fsi= 16 khz/ 44.1 khz fso/fsi= 8 khz/ 32 khz - 122 - 125 - 122 - 133 - 116 - 133 - 130 - 95 - 98 - 78 - 69 - 130 db db db db db db db db db db db db dynamic range (input=1khz, - 60dbfs) audio mode fso/fsi= 192 khz/48khz fso/fsi= 44.1 khz/48khz fso/fsi= 48 khz/ 88.2 khz fso/fsi= 48 khz/ 96 khz fso/fsi= 44.1 khz/ 96 khz fso/fsi= 48 khz/ 192 khz fso/fsi= 8 khz/ 48 khz voice mode fso/fsi= 24 khz/ 32 khz fso/fsi= 16 khz/ 24 khz fso/fsi= 24 khz/ 44.1 khz fso/fsi= 16 khz/ 44.1 khz fso/fsi= 8 khz/ 32 khz 132 136 135 136 136 136 130 132 135 132 128 130 db db db db db db db db db db db db dynamic range (input=1khz, - 60dbfs, a - weighted ) fso/fsi=44.1khz/48khz 1 37 db ratio between input and output sample rate fso/fsi 0.167 6 - note: * 11 . only two srcs are available out of src1 - 4 when the operation frequency is 192khz.
[ a k7707 ] 016011589 - e - 00 - pb 20 16/11 - 17 - spdif characteristics (ta = ? 40 ~ 85 oc , vdd33 = 3.13 ~ 3.47 v ) parameter symbol min typ . max . unit rx 0 input voltage level (internally biased at vdd33 / 2 ) input hysteresis input reference v oltage input r esistance input sampling frequency vih vil vty invref zin fs 100 - invref 8 50 vdd33 / 2 10 vdd33 - 100 96 mv mv mv v k ? digital micrephone interface (avdd=3.0 ~ 3.6v, t vdd= 1.7~ 3.6v, vdd 12 =1. 14~ 1. 3 v, avss=dvss=0v, ta= - 4 0 c ~ 85 c; cl= 10 0pf) parameter symbol m in . t yp . m ax . unit dmdat 1, dmdat2 serial data input latch set up time tdmds 50 ns serial data input latch hold time tdmdh 0 ns dmclk1, dmclk2 colock frequency ( * 12 ) fdmck 0.5 64fs 6.2 mhz duty ratio ddmck 40 50 60 % note: * 12 . clock frequency is determined by the sampling frequency (fs) that is selected by sddmic1[2:0] bits/sddmin2[2:0] bits current consumption (ta= 25 o c ; avdd= 3.0~3. 47 v( t yp . =3.3v, m ax . =3. 47 v) ; vdd33=3.0 ~ 3. 47 v ( t yp . =3.3v, m ax . =3. 47 v) ; vdd 12 = 1 . 14 ~ 1.3 v ( t yp . = 1.2 v, m ax . = 1.3 v) ; tvdd1= 1.7 ~ 3. 47 v ( t yp . =3.3v, m ax . =3. 47 v); tvdd2= 1.7 ~ 3. 47 v ( t yp . =3.3v, m ax . =3. 47 v ) ; vss1 ~ 6 = 0v ) parameter symbol m in . t yp . m ax . unit power - up ( * 13 ) (pdn pin= h) (pdn pin= l)
[ a k7707 ] 016011589 - e - 00 - pb 20 16/11 - 18 - 9. digital filter characteristics src block audio mode (ta = ? 40 ~ 85 o c; vdd12 = 1.14~1.3v; avdd = 3.13~3.47v; vdd33 = 3.13~3.47v; tvdd1 = 1.7~3.47v; tvdd2 = 1.7~3.47v; vss1~6 = 0v) notes: * 14 . calculated delay time in the src block only. this time is measured from a rising edge of lrck after a signal input to the src until a rising edge of lrck before a data output when there is no phase difference between input and output. parameter symbol m in . t yp . m ax unit passband - 0.01db 0.980 fso/fsi 6.000 pb 0 0.4583fsi khz - 0.01db 0.900 fso/fsi < 0.990 pb 0 0.4167fsi khz - 0.01db 0.533 fso/fsi < 0.909 pb 0 0.2182fsi khz - 0.01db 0.490 fso/fsi < 0.539 pb 0 0.2177fsi khz - 0.01db 0.450 fso/fsi < 0.495 pb 0 0.1948fsi khz - 0.01db 0.225 fso/fsi < 0.455 pb 0 0.1312fsi khz - 0.50db 0.167 fso/fsi < 0.227 pb 0 0.0658fsi khz stopband 0.980 fso/fsi 6.000 sb 0.5417fsi khz 0.900 fso/fsi < 0.990 sb 0.5021fsi khz 0.533 fso/fsi < 0.909 sb 0.2974fsi khz 0.490 fso/fsi < 0.539 sb 0.2812fsi khz 0.450 fso/fsi < 0.495 sb 0.2604fsi khz 0.225 fso/fsi < 0.455 sb 0.1802fsi khz 0.167 fso/fsi < 0.227 sb 0.0970fsi khz passband ripple 0.225 fso/fsi 6.000 pr 0.01 db 0.167 fso/fsi < 0.227 pr 0.50 db stopband attenuation 0. 450 fso/fsi 6.000 sa 95.2 db 0.167 fso/fsi < 0. 455 sa 85.0 db group delay (ts=1/fs) ( * 14 ) gd 6 7 (5 5 /fsi+1 2 /fso) ts
[ a k7707 ] 016011589 - e - 00 - pb 20 16/11 - 19 - voice mode (ta= - 40 ~ 85 o c; vdd12=1.14 ~ 1.3v; avdd=3.13 ~ 3.47v; vdd33=3.13 ~ 3.47v; tvdd1=1.7 ~ 3.47v; tvdd2=1.7 ~ 3.47v; vss1 ~ 6= 0v) echo canceller mode (ta= - 40 ~ 85 o c; vdd12=1.14 ~ 1.3v; avdd=3.13 ~ 3.47v; vdd33=3.13 ~ 3.47v; tvdd1=1.7 ~ 3.47v; tvdd2=1.7 ~ 3.47v; vss1 ~ 6= 0v) note: * 15 . this time is measured from a rising edge of lrck after a signal input to the src unt il a rising edge of lrck before a data output when there is no phase difference between input and output. * 16 . calculated delay time in the src block only. this time is measured from a rising edge of lrck after a signal input to the src until a rising edge of lrck before a data ou tput when there is no phase difference between input and output. parameter sym bol min. typ. max. unit passband - 0.01db 0.980 fso/fsi 6.000 pb 0 0.4583fsi khz - 0.01db 0.900 fso/fsi < 0.990 pb 0 0.4167fsi khz - 0.50db 0. 711 fso/fsi < 0.9 10 pb 0 0.3420fsi khz - 0.50db 0. 653 fso/fsi < 0. 718 pb 0 0.3007fsi khz - 0.50db 0.4 50 fso/fsi < 0. 660 pb 0 0.2230fsi khz - 0.50db 0. 327 fso/fsi < 0.455 pb 0 0.1417fsi khz - 0.50db 0.225 fso/fsi < 0. 330 pb 0 0.1018fsi khz - 0.50db 0.167 fso/fsi < 0.227 pb 0 0.0658fsi khz stopband 0.980 fso/fsi 6.000 sb 0.5417fsi khz 0.900 fso/fsi < 0.990 sb 0.5021fsi khz 0. 711 fso/fsi < 0.9 10 sb 0.3735fsi khz 0. 653 fso/fsi < 0. 718 sb 0.3320fsi khz 0.4 50 fso/fsi < 0. 660 sb 0.2490fsi khz 0. 327 fso/fsi < 0.455 sb 0.1660fsi khz 0.225 fso/fsi < 0. 330 sb 0.1248fsi khz 0.167 fso/fsi < 0.227 sb 0.0970fsi khz passband ripple 0.900 fso/fsi 6.000 pr 0.01 db 0. 167 fso/fsi 0.539 pr 0.50 db stopband attenuation 0.900 fso/fsi 6.000 sa 95.2 db 0. 6 53 fso/fsi < 0.909 sa 90.0 db 0.450 fso/fsi 0.660 sa 70.0 db 0.167 fso/fsi < 0. 455 sa 60.0 db group delay (ts=1/ fs) ( * 14 ) gd 67 (55fsi+12fso) ts parameter symbol min. typ. max. unit passband - 0.01db 0. 167 fso/fsi 6.000 pb 0 0.4583fsi khz stopband 0. 167 fso/fsi 6.000 sb 0.5417fsi khz passband ripple 0. 167 fso/fsi 6.000 pr 0.01 db stopband attenuation 0. 167 fso/fsi 6.000 sa 95.2 db group delay (ts=1/fs) ( * 14 ) gd 67 (55fsi+12fso) ts
[ a k7707 ] 016011589 - e - 00 - pb 20 16/11 - 20 - 10. dc characteristics dc characteristics (ta = ? 40 ~ 85 oc ; vdd 12 = 1 . 14 ~ 1.3 v; a vdd = 3.13 ~3. 47 v; vdd33 = 3.13 ~3. 47 v; tvdd1 = 1.7~3. 47 v; tvdd2 = 1.7~3. 47 v; v ss1~ 6 = 0v) parameter symbol m in . t yp . m ax . unit high - level input voltage 1 ( * 17 ) vih1 80%tvdd1 v low - level input voltage 1 ( * 17 ) vil1 20%tvdd1 v high - level input voltage 2 ( * 18 ) vih2 80%tvdd2 v low - level input voltage 2 ( * 18 ) vil2 20%tvdd2 v high - level input voltage 2 dmdat1/2 vih2dm 65 %tvdd2 v low - level input voltage 2 dmdat1/2 vil2dm 35 %tvdd2 v high - level input voltage 3 ( * 19 ) vih 3 80%vdd 33 v low - level input voltage 3 ( * 19 ) vil 3 20%vdd 33 v high - level input voltage a ( * 20 ) vih a 80% a vdd v low - level input voltage a ( * 20 ) vil a 20% a vdd v scl, sda high - level input voltage vih4 70%tvdd 1 v scl, sda low - level input voltage vil4 30%tvdd 1 v high - level input voltage iout= - 100 ? a ( * 17 ) voh1 tvdd1 - 0.3 v low - level input voltage iout= 100 ? a ( * 17 ) vol1 0.3 v high - level input voltage iout= - 100 ? a ( * 18 ) voh2 tvdd2 - 0.3 v low - level input voltage iout= 100 ? a ( * 18 ) vol2 0.3 v high - level input voltage iout= - 100 ? a ( * 19 ) voh 3 vdd 33 - 0.3 v low - level input voltage iout= 100 ? a ( * 19 ) vol 3 0.3 v high - level input voltage iout= - 100 ? a ( * 20 ) a voh a vdd - 0.3 v low - level input voltage iout= 100 ? a ( * 20 ) a vol 0.3 v scl, sda low - level output voltage fast mode tvdd2 2.0v (iout= 3ma) vol4 0.4 v tvdd2 < 2.0v (iout= 3ma) vol4 20%tvdd 1 v fast mode plus tvdd2 2.0v (iout= 1 0ma) ( * 21 ) vol4 0.4 v tvdd2 < 2.0v (iout= 3ma) vol4 20%tvdd 1 v input leak current ( * 22 ) iin 10 ? a input leak current, pulled down pin ( * 23 ) iid 80 ? a 4 3 k input leak current, xti pin lix 10 ? a notes: * 17 . sdin1, sdin2, sdout1, sdout2, lrck a , bick a , lrckb, bickb clko, pdn, sclk, so, csn, si/ i2cfil, sto / rdy and sele pin s. the scl and sda pins are not included. * 18 . sdin3, sdin4 /dmdat1 , sdin5/dmdat2, lrckd/dmclk1, bickd/dmclk2, sdout3/gpo 2 , sdout4, sdin5, lrck c , bick c , lrck d , gpio0/sdin7, gpio01/sdout7, gpio02/sdin8, gpio0 3/sdout8, esdo/gpio04, esclk/gpio05, esdi/gpio06 and ecso/gpio07 pin s. * 19 . tdo / gpo1, tdi/jx3, tms/jx2, tck/jx1, trst/jx0, sdin6 /rx1 , rx0, sdout5/gpo 3, dirint/gpo0, sdout6/dit , lrcke, bicke, testi1 and testi2 pin s. * 20 . at the xti pin in external input mode . * 21 . must be pulled up by 347 or more and connected to tvdd2. * 22 . internal pulled - down pins and the xti pin are not included. * 23 . for p ins with internal pull ed - down registers. (typ . 43 k @3.3v) . testi1 , bicke, lrcke, bickd/dmclk2, lrckd/dmclk1, lrckc, bickc, gpio00/sdin7, gpio01/sdout7, gpio02/sdin8, gpio03/sdout8, esdo/gpio04, esclk/gpio05, esdi/gpio06, ecso/gpio07, bickb,lrckb, lrcka,bicka, testi2, trst/jx0, tck/jx1, tms/jx2, tdi and jx3 pin s.
[ a k7707 ] 016011589 - e - 00 - pb 20 16/11 - 21 - 11. switching characteristics system clock (ta = - 40 ~ 85 oc ; vdd 12 = 1 . 14 ~ 1.3 v; a vdd = 3.13 ~3. 47 v; vdd33 = 3.13 ~3. 47 v; tvdd1 = 1.7~3. 47 v; tvdd2= 1.7~3. 47 v; v ss1~ 6 = 0v; c l = 20pf) parameter symbol m in . t yp . m ax . unit xti input timing a) xtal oscillator clko output timing output frequency fclko 2.048 24.576 mhz duty cycle dclko 50 % lrck/bick input timing (slave mode) lrck input timing frequency fs 8 192 khz bick input timing frequency ( * 24 ) fbclk 0.256 24.576 mhz duty cycle d bclk 40 50 60 % lrck/bick output timing (pll master mode) lrck output timing frequency fs 8 192 khz pulse width high pcm mode except pcm mode tlrckh tlrckh 1/fbclk 50 s % bick output timing frequency ( * 24 ) fbclk 0.256 24.576 mhz duty dbclk 50 % note: * 24 . this value must be fbc l k 2 x fs x ( input/ output data length ) . power down (ta = ? 40 ~ 85 oc ; vdd 12 = 1 . 14 ~ 1.3 v; a vdd = 3.13 ~3. 47 v; vdd33 = 3.13 ~3. 47 v; tvdd1 = 1.7~3. 47 v; tvdd2 = 1.7~3. 47 v; v ss1~ 6 = 0v ) parameter symbol min . t yp . m ax . unit pdn pulse width ( * 25 ) trst 600 ns note: * 25 . the pdn pin must be l when power up the ak7707. figure 5 . reset timing vil 1 trst pdn t rsp
[ a k7707 ] 016011589 - e - 00 - pb 20 16/11 - 22 - serial data interface (sdin1~ sdin 8 , sdout1~ sdout 8 ) (ta = ? 40 ~ 85 oc ; vdd 12 = 1 . 14 ~ 1.3 v; a vdd = 3.13 ~3. 47 v; vdd33 = 3.13 ~3. 47 v; tvdd1 = 1.7~3. 47 v; tvdd2 = 1.7~3. 47 v; v ss1~ 6 = 0v; c l =20pf) parameter symbol m in . t yp . m ax . unit slave mode delay time from bick bick delay time from bick when the bick polarity is inverted by setting bckpx bit = 1 . * 27 . m easured from bick when the bick polarity is inverted by setting bckpx bit = 1 . * 28 . set sdophx bit to 1 and the data should be output based on bick if bick is faster than 12.288mhz such as when using tdm256 mode with 96khz sampling frequency in slave mode. sdophx bit must be set to 0 in master mode.
[ a k7707 ] 016011589 - e - 00 - pb 20 16/11 - 23 - 1. slave mode figure 6 . serial interface input timing in slave mode figure 7 . serial interface output timing in slave mod e (sdophx bit = 0 ) figure 8 . serial interface output timing in slave mod e (sdophx bit = 1) tbsids tblrd tlrbd d vih d vil d tbsidh sdin 1 ~ 6 lrck(i) bick(i) vih d vil d vih d vil d vih lrck (i) bick (i) vil sdout 1~ 6 50% t vdd 1/ 2 tbsod 1 d vih vil 50% vdd33 tblrd tlrbd d tbsod1 d vih lrck (i) bick (i) vil sdout 1~ 6 50% t vdd 1/ 2 tbsod 2 d vih vil 50% vdd33 tblrd tlrbd d tbsod 2 d
[ a k7707 ] 016011589 - e - 00 - pb 20 16/11 - 24 - 2. master mode figure 9 . serial interface input timing in master mode figure 10 . serial interface output timing in master mode tbsids tmbl tmbl d lrck (o) bick(o) vih d vil tbsidh sdin1 ~ 6 50%tvdd1/2 50% vdd33 50%tvdd1/2 50% vdd33 tbsod d lrck (o) bi ck (o) sdout 1~6 50%tvdd1/2 50% vdd33 50%tvdd1/2 50% vdd33 50%tvdd1/2 50% vdd33 tbsod d
[ a k7707 ] 016011589 - e - 00 - pb 20 16/11 - 25 - spi interface 1 . clock reset (ckresetn bit = 0) (ta = ? 40 ~ 85 oc ; vdd 12 = 1 . 14 ~ 1.3 v; a vdd = 3.13 ~3. 47 v; vdd33 = 3.13 ~3. 47 v; tvdd1 = 1.7~3. 47 v; tvdd2 = 1.7~3. 47 v; v ss1~ 6 = 0v; c l = 20pf) parameter symbol m in . t yp . m ax . unit p interface csn pdn pdn csn csn sclk sclk csn so output hold time from sclk 2 . pll lock (ckresetn bit = 1 and pll is locked ) (ta = ? 40 ~ 85 oc ; vdd 12 = 1 . 14 ~ 1.3 v; a vdd = 3.13 ~3. 47 v; vdd33 = 3.13 ~3. 47 v; tvdd1 = 1.7~3. 47 v; tvdd2 = 1.7~3. 47 v; v ss1~ 6 = 0v; c l = 20pf) parameter symbol m in . t yp . m ax . unit p interface csn pdn pdn csn csn sclk sclk csn so output hold time from sclk ckresetn bit = 0 1 . control registers can always be accessed by 7mhz.
[ a k7707 ] 016011589 - e - 00 - pb 20 16/11 - 26 - figure 11 . spi interface timing 1 figure 12 . spi interface timing 2 (microcontroller ak77 07 ) figure 13 . spi interface timing 3 ( ak77 07 microcontroller) tsclkh tsclkl 1/fsclk 1/fsclk sclk vih 1 vil 1 vih 1 vil 1 vih 1 vil 1 trst pd n csn tirrq twrqh tsis tsih tscw tscw twsc tscw cs n si vih 1 vil 1 vih 1 twsc sclk vil 1 vih 1 vil 1 tsos tsoh sclk vil 1 vih 1 so vih 1 vil 1
[ a k7707 ] 016011589 - e - 00 - pb 20 16/11 - 27 - i 2 c interface (ta = ? 40 ~ 85 oc ; vdd 12 = 1 . 14 ~ 1.3 v; a vdd = 3.13 ~3. 47 v; vdd33 = 3.13 ~3. 47 v; tvdd1 = 1.7~3. 47 v; tvdd2 = 1.7~3. 47 v; v ss1~ 6 = 0v; c l = 20pf) parameter symbol m in . t yp . m ax . unit i 2 c timing scl clock frequency fscl - - 400 khz bus free time between transmissions tbuf 1.3 - - ? ? ? ? ? ? ? ? ? ? 2 c: fast mode plus> parameter symbol m in . t yp . m ax . unit i 2 c timing scl clock frequency fscl - - 1 mhz bus free time between transmissions tbuf 0.5 - - ? ? ? ? ? ? ? ? ? ? 2 c - bus interface timing thigh scl sda vih 4 tlow tbuf thd:sta t r tf thd:dat tsu:dat tsu:sta stop start start stop tsu:sto vil 4 vih 4 vil 4 tsp
[ a k7707 ] 016011589 - e - 00 - pb 20 16/11 - 28 - master spi interface (ta= - 40 ~ 85 oc ; vdd 12 = 1 . 14 ~ 1.3 v; a vdd= 3.13 ~ 3. 47 v; vdd33=3.13 ~ 3. 47 v; tvdd1=1.7 ~ 3. 47 v; tvdd2= 1.7 ~ 3. 47 v; v ss1 ~ 6= 0v; c l = 20pf) parameter symbol m in . t yp . m ax . unit master mode sclk frequency ( * 31 ) - 6.144 mhz sclk duty ( * 32 ) - 50 % ecso x tal low er than 12.288mhz is supported. * 32 . when dividing number is even. jtag interface (ta= - 40 ~ 85oc ; vdd 12 = 1 . 14 ~ 1.3 v; a vdd= 3.13 ~ 3. 47 v; vdd33=3.13 ~ 3. 47 v; tvdd1=1.7 ~ 3. 47 v; tvdd2= 1.7 ~ 3. 47 v; v ss1 ~ 6= 0v ; c l = 20pf) parameter symbol m in . t yp . m ax . unit tck frequency 7 mhz tck pulse width l o w 60 n s tck pulse width high 60 n s tms setup t i me from tck rising 60 n s tms hold time from tck rising 60 n s tdi setup time from tck rising 60 n s tdi hold time from tck rising 60 n s trst setup time from tck rising 60 n s from trst
[ a k7707 ] 016011589 - e - 00 - pb 20 16/11 - 29 - 12. recommended external circuits connection diagram figure 15 . system connection diagram d igital +1.2 v clko bick d xto xti rd c l c l 36 11 5 0 2 9 cs n sda / so i2cfil 3 1 3 0 micom i/f 8,21,37,43 , 52, 5 7 58 digital 3.3 v pdn vdd 33 reset control ak77 07 vss lrck a 47 b i ck a 4 8 10 ? audio i/f 10 ? 0.1 ? vdd 12 3 lrck d 12 clock 3 3 0.1 ? 7 scl / sclk l rc k b b ick b 40 39 l rck c b ick c 16 17 & sdout1 sdout 2 sdout 3 sdin1 sdin 2 46 41 14 42 sdin3 15 45 3 2 34 sto 2 testi1 0.1 ? 22 4 9 55 testi 2 sdout 4 13 sdin 4 10 sdin 5 9 sdout 5 5 jx0 6 0 20 digital 1.8 3.3v tvdd2 10 ? 0.1 ? sdin6/rx1 5 9 sdout6/dit 1 44 0.1 ? 38 digital 1.8 3.3v tvdd1 10 ? 0.1 ? testa2 54 51 analog 3.3v avdd 10 ? 0.1 ? t esta1 53 sele 3 5
[ a k7707 ] 016011589 - e - 00 - pb 20 16/11 - 30 - peripheral circuit 1. ground all vss should be connected to the same analog ground. decoupling capacitors, pa rticularly ceramic capacitors of small capacity, should be placed at positions as close as possible to the ak77 07 . 2. connection to digital circuit to minimize the noise from digital circuits, the digital output of the ak 77 07 must be connected to cmos or low voltage logic ics such as 74hc and 74ac for cmos and 74lv, 74lv - a, 74alvc and 74avc for low voltage logic ics. 3. cristal oscillator the resistor and capacitor values fo r the oscillator rc circuit are shown b e low. xtal oscillator r1 ( m ax . ) c0 ( m ax . ) xti, xto pin capacity (cl) 12.288mhz 80 80
[ a k7707 ] 016011589 - e - 00 - pb 20 16/11 - 31 - 13. packag e outline dimensions 64 - pin ht qfp (unit: mm) material and lead finish package: epoxy lead frame: copper lead - finish: soldering (pb free) plate 0 . 05 ~ 0 . 15 1 . 00 0 . 05 1 . 2 max 0 . 10 s 0 . 22 0 . 05 1 ( 4 . 68 ) ( 4 . 68 ) 12 . 0 0 . 20 12 . 0 0 . 20 0 . 50 16 17 32 33 48 49 64 10 . 0 0 . 20 10 . 0 0 . 20 0 . 60 0 . 15 0 . 09 ~ 0 . 2 c m 0 . 10 s a c a s
[ a k7707 ] 016011589 - e - 00 - pb 20 16/11 - 32 - marking 1) pin #1 indication 2) date code: xxxxxxx (7 digits) 3) marking code: ak7707 vq 4) asahi kasei logo 14. ordering guide ordering guide ak77 07vq - 40 ? +85 o c 64 - pin ht qfp (0.5mm pitch) akd77 07 evaluation board for ak7707 a k7707vq xxxxxxx akm
[ a k7707 ] 016011589 - e - 00 - pb 20 16/11 - 33 - important notice 0. asahi kasei microdevices corporation (akm) reserves the right to make changes to the information contained in this document without notice. when you consider any use or application of akm product stipulated in this document ( product ) , please make inquiries the sales office of akm or authorized distributor s as to current status of the products. 1. all information included in this document are provided only to illustrate the operation and application examples of akm products . akm neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of akm or any third party with respect to the information in this document. you are fully responsible for use of such information contained in this document in your product design or applications . akm assumes no liability for any losses incurred by you or third parties arising from the use of such information in your product design or applications. 2. the product is neither intended nor warranted for use in equipment or systems that r equire extraordinarily high levels of quality and/or reliability and/or a malfunction or failure of which may cause loss of human life, bodily injury, serious property damage or serious public impact , including but not limited to, equipment used in nuclear facilities, equipment used in the aerospace industry, medical equipment, equipment used for automobiles, trains, ships and other transportation, traffic signaling equipment, equipment used to control combustions or explosions, safety devices, elevators an d escalators, devices related to electric power, and equipment used in finance - related fields. do not use product for the above use unless specifically agreed by akm in writing . 3. though akm works continually to improve the products quality and reliabili ty, you are responsible for complying with safety standards and for providing adequate designs and safeguards for your hardware, software and systems which minimize risk and avoid situations in which a malfunction or failure of the product could cause loss of human life, bodily injury or damage to property, including data loss or corruption. 4. do not use or otherwise make available the product or related technology or any information contained in this document for any military purposes, including without l imitation, for the design, development, use, stockpiling or manufacturing of nuclear, chemical, or biological weapons or missile technology products (mass destruction weapons). when exporting the p roducts or related technology or any information contained in this document, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations. the p roducts and related technology may not be used for or incorporated into any products or system s whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. 5. please contact akm sales representative for details as to environmental matters such as the rohs compatibility of the product. please use the p roduct in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the eu rohs directive. akm assumes no liability for damages or losses occurring as a result of noncompl iance with applicable laws and regulations. 6. resale of the product with provisions different from the statement and/or technical features set forth in this document shall immediately void any warranty granted by akm for the product and shall not create o r extend in any manner whatsoever , any liability of akm. 7. this document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of akm .
[ a k7707 ] 016011589 - e - 00 - pb 20 16/11 - 34 - thank you for your acce ss to akm product s information . more detail product inform ation is available, please contact our sales office or authorized distributors.

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